Analog-to-digital converter

ABSTRACT

An analog-to-digital converter for converting an analog input signal to a digital output signal with m upper bits and n lower bits includes at least 2 m+n  -1 resistors connected in a series circuit to a voltage source for establishing respective reference voltages; switch elements selectively coupled to the analog input signal and the resistors in response to a switch control signal for supplying a signal indicative of the analog input signal and the respective reference voltages; at least 2 m  -1 upper bit comparators for generating the switch control signal and output signals indicative of the m upper bits, with first inputs receiving the analog input signal and second inputs connected to the series circuit at intervals defining groups of the resistors; an upper bit encoder receiving the output signals from the upper bit comparators and generating the m upper bits; at least 2 n  -1 lower bit comparators for generating output signals indicative of the n lower bits, having first and second inputs connected to the switch elements whereby the switch elements selectively supply the signal indicative of the analog input signal to the first inputs and selectively connect the second inputs to the respective resistors in response to the switch control signal; and a lower bit encoder receiving the output signal from the lower bit comparators for generating the n lower bits.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to an analog-to-digital converter, and moreparticularly, to a compact, high speed analog-to-digital converter.

2. Description of the Prior Art

Prior art analog-to-digital converters can generally be classified aseither parallel-type converters or serial-to-parallel type converters.

Parallel-type analog-to-digital converters which produce n bit digitaloutputs generally require (2^(n) -1) comparing circuits or comparatorsconnected in parallel. An analog input voltage is supplied to the (2^(n)-1) voltage comparators, and the outputs from the comparators aresupplied to an encoder which then produces the n digit output.

In a serial-to-parallel type analog-to-digital converter having anoutput of m upper bits and n lower bits, the input voltage is suppliedto a first stage of (2^(m) -1) voltage comparing circuits orcomparators, just as in the parallel-type analog-to-digital converter,to generate the m upper bits. The m upper bits are then supplied to adigital-to-analog converter and reconverted to an analog voltage. Thereconverted analog voltage is then subtracted from the analog inputvoltage and the difference is supplied to a second stage of (2^(n) -1)voltage comparators to derive the n lower bits.

In the parallel-type analog-to-digital converter, (2^(n) -1) voltagecomparators are required when the analog input voltage is converted to adigital output of n bits. A large number of circuit elements arerequired for such an analog-to-digital converter, and the resultingintegrated circuit is large and has a correspondingly large powerconsumption.

In the serial-to-parallel analog-to-digital converter, only (2^(m)+2^(n) -2) voltage comparators are used when the output has m +n bits.The chip size and power consumption are reduced as compared to theparallel-type analog-to-digital converter. However, a serial-to-parallelanalog-to-digital converter requires a digital-to-analog converter. Ifan error occurs between the first and second stages of the converter,the error is repeated in the digital output. For example, with amonotonically increasing voltage V_(in), if an error occurs between thefirst and second stages so that the output from the first stage isreduced, the digital output from the second stage will be reduced, andthe digital output of the converter will not increase monotonically.

OBJECTS AND SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide ananalog-to-digital converter which does not have the aforesaid problemsof prior art analog-to-digital converters.

It is another object of the present invention to provide ananalog-to-digital converter on a semiconductor pellet which is acompact, integrated circuit.

It is still another object of the present invention to provide a highspeed analog-to-digital converter.

It is still a further object of the present invention to provide a lowpower consumption analog-to-digital converter.

In accordance with one aspect of the present invention, ananalog-to-digital converter for converting an analog input signal to adigital output signal of m upper bits and n lower bits includes at least2^(m+n) -1 resistors connected in a series circuit to a voltage sourcefor establishing respective reference voltages. Switch elements areselectively coupled to the analog input signal and the resistors by aswitch control signal and supply a signal indicative of the analog inputsignal and the reference voltages. A plurality of upper bit comparatorsfor generating the switch control signal and output signals indicativeof the m upper bits have first inputs receiving the analog input signaland second inputs connected to the series circuit at intervals defininggroups of the resistors. An upper bit encoder receives the outputsignals from the upper bit comparators and generates the m upper bits. Aplurality of lower bit comparators for generating outputs indicative ofthe n lower bits have first and second inputs connected to the switchelements whereby the switch elements selectively supply the signalindicative of the analog input signal to the first inputs of the lowerbit comparators and selectively connect the second inputs to therespective resistor groups in response to the switch control signal. Alower bit encoder receives the outputs from the lower bit comparatorsand generates the n lower bits.

The above, and other objects, features and advantages of the inventionwill be apparent from the following detailed description of illustrativeembodiments thereof which is to be read in connection with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a prior art parallel-typeanalog-to-digital converter;

FIG. 2 is a block diagram illustrating a prior art serial-to-parallelanalog-to-digital converter;

FIG. 3 illustrates an embodiment of an analog-to-digital converter inaccord with the present invention;

FIGS. 4A and 4B are truth tables of encoders illustrated in FIG. 3;

FIG. 5 is a block diagram illustrating an alternate embodiment of ananalog-to-digital converter in accord with the invention;

FIG. 6 is a block diagram illustrating an arrangement of circuitelements on an integrated circuit chip of an analog-to-digital converterin accord with the present invention;

FIG. 7 is a detailed block diagram illustrating the analog-to-digitalconverter of FIG. 6;

FIG. 8 is a sectional block diagram of an alternate arrangement ofresistors and voltage comparators in an analog-to-digital converter andto which reference will be made in explaining the advantages thereoverof the arrangements according to the invention; and

FIG. 9 is another sectional block diagram of an alternate arrangement ofcircuit elements of an analog-to-digital converter on an integratedcircuit chip, and to which reference will be made in explaining theadvangtages thereover of the arrangements according to the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring initially to FIG. 1, a parallel-type analog-to-digitalconverter known in the prior art is disclosed in which an analog inputvoltage V_(in) is converted to an 8 bit digital output D₀ to D₇. Theparallel-type analog-to-digital converter of FIG. 1 has 255 voltagecomparing circuits or comparators A₁ to A₂₅₅, providing 255 referencevoltage steps V₁ to V₂₅₅. Analog input voltage V_(in) is compared witheach of reference voltages V₁ to V₂₅₅, and outputs from comparatorcircuits A₁ to A₂₅₅ are supplied to an encoder ENC which generatesdigital outputs D₀ to D₇.

In FIG. 2, a serial-to-parallel type analog-to-digital converter isshown in which analog input voltage V_(in) is converted to a digitaloutput voltage of n lower bits and m upper bits. In the illustrativeembodiment, the n lower bits are denoted as D₀ to D₃, while the m upperbits are denoted as D₄ to D₇. Input voltage V_(in) is supplied to afirst or front stage of the serial-to-parallel type analog-to-digitalconverter having comparison circuits or comparators A_(1m) to A_(15m)and corresponding voltage steps V_(1m) to V_(15m), from which outputsare supplied to upper bit encoder ENCM which generates m upper bits D₄to D₇. Upper bits D₄ to D₇ are supplied to a digital-to-analog converterCONV where they are reconverted to an analog voltage V_(m). Analogvoltage V_(m) is then subtracted from input voltage V_(in), and thedifference is supplied to a second or rear stage of theserial-to-parallel type analog-to-digital converter. The second stagehas comparison circuits A_(1n) to A.sub. 15n and corresponding voltagesteps V_(1n) to V_(15n), and supplies outputs to a second encoder ENCN,which generates n lower bits D₀ to D₃.

Referring to the embodiment of the invention illustrated in FIG. 3,three upper bit voltage comparators or coarse comparators M₁, M₂, and M₃are arranged on one side of resistors R₀ to R₁₅ and have emitters oftransistors Q_(m1) and Q_(m2) connected together to a constant currentsource S_(m). Three lower bit voltage comparators or fine comparatorsN₁, N₂ and N₃ are arranged on another side of resistors R₀ to R₁₅ andhave emitters of transistors Q_(n1) and Q_(n2) connected together to aconstant current source S_(n).

Voltage comparators A_(ij) (where i equals 1 to 4 and j equals 1 to 3)have emitters of transistors Q₁ and Q₂ connected together to a collectorof a current switching transistor Q₃. Each row of voltage comparatorsA_(i1) to A_(i3) (i equals 1 to 4) functions as a first stage comparatorof fine comparators N₁, N₂ and N₃, since analog input voltage V_(in) iscompared to reference voltages V_(i) (i equals 1 to 15) in voltagecomparators A_(i1) to A_(i3).

Resistors R₀ to R₁₅ having equivalent resistance values are connected inseries as a resistor string between a reference voltage source V_(r) andground to supply sixteen reference voltages V₀ to V₁₅. Every fourth stepof the reference voltages V₀ to V₁₅, i.e., voltages V₄, V₈ and V₁₂, aresupplied to bases of transistors Q_(m1) in coarse comparators M₁, M₂ andM₃. Voltages V₁₃ to V₁₅ and V₅ to V₇ are supplied to bases oftransistors Q₂ in coarse comparators A_(2j) and A_(4j) (j equals 1 to3). Voltages V₉ to V₁₁ and V₁ to V₃ are supplied to bases of transistorsQ₁ of voltage comparators A_(1j) and A_(3j) (j equals 1 to 3). Analoginput voltage V_(in) is supplied to bases of transistors Q_(m2) ofcoarse comparators M₁, M₂ and M₃, to bases of transistors Q₂ of voltagecomparators A_(1j) (j equals 1 to 3) and A_(3j) (j equals 1 to 3), andto bases of transistors Q₁ of voltage comparators A_(2j) (j equals 1 to3) and A_(4j) (j equals 1 to 3).

A collector output P₃ of transistor Q_(m1) of coarse comparator M₃ issupplied to the bases of transistors Q₃ of voltage comparators A_(4j) (jequals 1 to 3). A wired-AND output P₂ from outputs of collectors oftransistor Q_(m2) of coarse comparator M₃ and transistor Q_(m1) ofcoarse comparator M₂ is supplied to bases of transistors Q₃ ofcomparator A_(3j) (j equals 1 to 3). A wired-AND output P₁ from outputsof collectors of transistors Q_(m2) of coarse comparator M₂ andtransistor Q_(m1) of coarse comparator M₁ is supplied to bases oftransistors Q₃ of comparator A_(2j) (j equals 1 to 3). A collectoroutput P₀ of transistor Q_(m2) of coarse comparator M₁ is supplied tobases of transistors Q₃ of comparator A_(1j) (j equals 1 to 3). Emittersof transistors Q₃ of comparators A_(i1) (i equals 1 to 4) are connectedto constant current source S₁. Emitters of transistors Q₃ of comparatorsA_(i2) (i equals 1 to 4) are connected to constant current source S₂.Emitters of transistors Q₃ of comparators A_(i3) (i equals 1 to 4) areconnected to constant current source S₃. Outputs P₁ to P₃ of coarsecomparators M₁ to M₃ are supplied to an upper bit encoder or coarseencoder ENCM which generates upper bits D₂ and D₃ of the digital output.Coarse bit encoder ENCM also supplies a control signal to a lower bit orfine bit encoder ENCN, as will be described more fully hereinbelow.

Collectors of transistors Q₁ and Q₂ of comparators A_(i1) to A_(i3) (iequals 1 to 4) are connected to bases of transistors Q_(n1) and Q_(n2),respectively, of fine comparators N₁ to N₃. A collector output B₃ oftransistor Q_(n1) of fine comparator N₃ is supplied to fine bit encoderENCN. A wired-AND output B₂ from outputs of collectors of transistorQ_(n2) of fine comparator N₃ and transistor Q_(n1) of fine comparator N₂is supplied to fine bit encoder ENCN. A wired-AND output B₁ from theoutputs of collectors of transistor Q_(n2) of comparator N₂ andtransistor Q_(n1) of comparator N₁ is supplied to fine bit encoder ENCN.Bit D₂ from coarse bit encoder ENCM is also supplied to fine bit encoderENCN, and its function will be described more fully below. Fine bitencoder ENCN supplies lower 2-bits D₀ and D₁ of the digital output.

FIG. 4A illustrates the truth tables for the coarse bit encoder ENCM,while FIG. 4B illustrates the truth tables for fine bit encoder ENCN.The truth table of FIG. 4A indicates the values of bits D₂ and D₃ forgiven values of outputs P₀ to P₃. The truth table of FIG. 4B indicatesthe values of bits D₀ and D₁ for given values of outputs B₁ to B₃ andbit D₂.

The operation of the illustrative embodiment will now be described withreference to FIG. 3, in which an analog input voltage V_(in) is lessthan reference voltage V₇, is greater than reference voltage V₆, and isequal to the reference voltage at the point 1 between resistors R₆ andR₇ of FIG. 3. For the following description, the letters "H" and "L" areused to indicate the high or low levels, respectively, of a signal, andinclude a subscript 1 to indicate the reference voltage V_(in) at point1.

Since analog input voltage V_(in) is less than reference voltage V₈ andfurther less than reference voltage V₁₂, the bases of transistors Q_(m1)of coarse comparators M₂ and M₃ become "H₁ ", and the bases oftransistors Q_(m2) of coarse comparators M₂ and M₃ become "L₁ ", so thatthe collectors of transistors Q_(m1) become "L₁ ". Since analog inputvoltage V_(in) is greater than reference voltage V₄, the base oftransistor Q_(m1) of coarse comparator M₁ becomes "L₁ ", and the base oftransistor Q_(m2) becomes "H₁ ", so that the collector of transistorQ_(m1) becomes "H₁ " and the collector of transistor Q_(m2) becomes "L₁". With collector output P₀ equal to "L₁ ", collector output P₁ equal to"H₁ ", collector outputs P₂ and P₃ equal to "L₁ " (from the operation ofthe wired-AND between "L₁ " and "H₁ " producing an output of "L₁ "), thesecond row of the truth table of FIG. 4A indicates that bit D₂ is equalto "1", and bit D₃ is equal to "0".

With collector outputs P₀ to P₃ equal to "L₁ ", "H₁ ", "L₁ " and "L₁ ",respectively, transistors Q₃ of comparators A_(2j) (j equals 1 to 3) aremade on, so that analog input voltage V_(in) is compared with referencevoltages V₅ to V₇ in comparators A_(2j). Since analog input voltageV_(in) is less than reference voltage V₇ and greater than referencevoltage V₆, the base of transistor Q₁ of comparator A₂₃ becomes "L₁ ",and the base of transistor Q₂ becomes "H₁ ", so that the collector oftransistor Q₁ becomes "H₁ " and the collector of transistor Q₂ becomes"L₁ ". With the bases of transistors Q₁ of comparators A₂₁ and A₂₂ equalto "H₁ ", and the bases of transistors Q₂ equal to "L₁ ", the collectorsof transistors Q₁ become "L₁ " and the collectors of transistors Q₂become "H₁ ".

The above-identified outputs are supplied to fine comparators N₁ to N₃,so that the collector of transistor Q_(n1) of fine comparator N₃ becomes"L₁ ", the collector of transistor Q_(n2) becomes "H₁ ", the collectorsof transistors Q_(n1) of fine comparators N₁ and N₂ become "H₁ ", andthe collectors of transistors Q_(n2) become "L₁ ". Accordingly,collector output B₁ is equal to "L₁ ", collector output B₂ is equal to"H₁ ", and collector output B₃ is equal "L₁ ". The seventh row of thetruth table of FIG. 4B indicates that bit D₁ is equal to "1" and bit D₀is equal to "0" when bit D₂ is equal to "1".

As a check on the above calculation, it is to be noted that analog inputvoltage V_(in) is the sixth step in the series circuit of resistors,with the zero step being the ground side. The decimal number six is thebinary number "0110". From the discussion above, the digital outputs D₃to D₀ are "0110".

By way of a second example, analog input voltage V_(in) is equal to theelectric potential in the series circuit of resistors R₀ to R₁₅ at thepoint 2, and is less than reference voltage V₁₀ and greater thanreference voltage V₉.

Since analog input voltage V_(in) is less than reference voltage V₁₂,the base of transistor Q_(m1) of coarse comparator M₃ becomes "H₂ ", andthe base of transistor Q_(m2) becomes "L₂ ", so that the collector oftransistor Q_(m1) becomes "L₂ " and the collector of transistor Q_(m2)becomes "H₂ ". Since analog input voltage V_(in) is greater thanreference voltages V₈ and V₄, the bases of transistors Q_(m1) ofcomparators M₁ and M₂ become "L₂ " and the bases of transistors Q_(m2)become "H₂ ", so that the collectors of transistors Q_(m1) become "H₂ "and the collectors of transistors Q_(m2) become "L₂ ". Accordingly,collector output P₀ is equal to "L₂ ", collector output P₁ is equal to"L₂ ", collector output P₂ is equal to "H₂ ", and collector output P₃ isequal to "L₂ ". From the third row of the truth table of FIG. 4A,digital output D₃ is equal "1" and digital output D₂ is equal "0".

With the collector outputs P₀ to P₃ equal to "L₂ ", "L₂ ", "H₂ " and "L₂", respectively, only transistors Q₃ of comparators A_(3j) (j equals 1to 3) are made on, so that analog input voltage V_(in) is compared withreference voltages V₉ to V₁₁ in comparators A_(3j). Since analog inputvoltage V_(in) is greater than reference voltage V₉ and less thanreference voltage V₁₀, the base of transistor Q₁ of comparator A₃₃becomes "L₂ ", the base of transistor Q₂ becomes "H₂ ", so that thecollector of transistor Q₁ becomes "H₂ " and the collector of transistorQ₂ becomes "L₂ ". The bases of transistors Q₁ of comparators A₃₁ and A₃₂become "H₂ ", and the bases of transistors Q₂ become "L₂ ", so that thecollectors of transistors Q₁ become "L₂ " and the collectors oftransistors Q₂ become "H₂ ".

With the above-mentioned outputs supplied to fine comparators N₁ to N₃,the collector of transistor of Q_(n1) of fine comparator N₃ is "L₂ ",the collector of transistor Q_(n2) of fine comparator N₃ is "H₂ ", thecollectors of transistors Q_(n1) of fine comparators N₂ and N₁ become"H₂ ", and the collectors of transistors Q_(n2) of fine comparators N₁and N₂ become "L₂ ". With outputs B₁ to B₃ equal to "L₂ ", "H₂ " and "L₂", respectively, from the operation of the wired-AND outputs B₂ and B₁,the second row of the truth table of FIG. 4B indicates digital output D₁is equal to "0" and digital output D₀ is equal "1", when digital outputD₂ is equal to "0".

The accuracy of the values for outputs D₃ to D₀ can be confirmed bynoting that analog input voltage V_(in) is the ninth step of the seriescircuit of resistors R₀ to R₁₅. Decimal number nine is the same asbinary number "1001", which corresponds to digital outputs D₃ to D₀.

When an analog-to-digital converter is formed with resistors R₀ to R₁₅in a zigzag pattern, the reference voltage increases from left to right,as shown in FIG. 3, in resistor strings R₀ to R₃ and R₈ to R₁₁(hereinafter referred to as group A), and decreases from left to rightin resistor strings R₄ to R₇ and R₁₂ to R₁₅ (hereinafter referred to asgroup B). Since the reference bias conditions of the resistor strings ofgroup A differ from those of the resistor strings of group B, finecomparators N₁, N₂ and N₃ should be accordingly interchanged when thedifferent groups are connected by the respective switch assembliesA_(ij). In the illustrated embodiment, digital outputs D₁ and D₀ areinverted in response to the value of bit D₂ from upper bit encoder ENCM,rather than physically interchanging fine comparators N₁, N₂ and N₃ .

In the above second example in which analog input voltage V_(in) isequal to an electric potential at the connection point between resistorsR₉ and R₁₀, as shown at point 2 in FIG. 3, as described above, upper bitencoder ENCM will generate control signal P₂ equal to "H₂ " to coupleresistors R₉ to R₁₁ to fine comparators N₁, N₂ and N₃ .

However, in the second example, when the analog-to-digital converter isformed on an integrated circuit chip, the distance on the chip from theresistor R₈ to point 2 is the same as the distance from the resistor R₇to point 1 of the first example, and the voltage differences are thesame. Accordingly, digital outputs D₀ and D₁ must be inverted to become"1" and "0", respectively.

According to the analog-to-digital converter of the present invention,reference voltages V₀ to V₁₅ are divided into four groups comprising V₀to V₃, V₄ to V₇, V₈ to V₁₁ and V₁₂ to V₁₅. Each of voltages V₄, V₈ andV₁₂, representing the four groups, is compared with analog input voltageV_(in) to derive the upper two bits D₂ and D₃ of the digital output.Voltage groups V_(k) to V_(k-3) (were k equals 3, 7, 11 and 15) areselected in response to the upper two bits D₂ and D₃. Voltages V_(k) toV_(k-2) are then compared with analog input voltage V_(in) to derivelower 2-bits D₀ and D₁ of the digital output.

Accordingly, the analog-to-digital converter of the present inventionuses fewer comparators as compared to the parallel-typeanalog-to-digital converter of the prior art. If there are m upper bitsof digital output and n lower bits of digital output, the number ofcoarse comparators is 2^(m) -1 and the number of fine comparators is2^(n) -1. Since voltage comparators A_(ij) are first stage-circuits infine comparators N₁ to N₃ and also switching elements, the number oftransistors used is also reduced. Both the semiconductor pellet size andthe power consumption can be accordingly reduced when theanalog-to-digital converter of the present invention is formed as anintegrated circuit.

Since reference voltages V₀ to V₁₅ are used for deriving both the upperbits D₂ and D₃ and the lower bits D₀ and D₁, the likelihood of an errorbetween the upper bits D₂ and D₃ and the lower bits D₀ and D₁ issignificantly reduced, unlike prior art serial-to-parallelanalog-to-digital converters, where an error between the front and rearstages can produce an error between the upper bits derived from thefront stage and the lower bits derived from the rear stage.

In a preferred embodiment, the analog-to-digital converter of FIG. 3 canbe made of bipolar transistors with a high driving frequency, so that ananalog video signal can be converted to a digital output. Bipolartransistors are also superior to metal oxide semiconductor-field effecttransistors, since MOS-FETs have a slow switching operation withoutproducing an increase in the accuracy of the comparator.

FIG. 5 illustrates a desirable circuit arrangement according to theinvention in which the coarse comparator M₂ of the analog-to-digitalconverter of FIG. 3 has been moved to the opposite or left-hand side ofthe comparators A_(ij), and the lower bit encoder ENCM has been moved toa position adjacent upper bit encoder ENCN. The illustrated arrangementof the analog-to-digital converter on an integrated circuit chip resultsin a more compact analog-to-digital converter than the one depicted inFIG. 3, and also decreases parasitic capacities between signal lines.

FIG. 6 illustrates an arrangement of elements in a circuit on asemiconductor chip SP for an 8-bit analog-to-digital converter in accordwith the present invention. Analog input voltage V_(in) is converted toan upper 4 bit output and a lower 4 bit output. Accordingly, theillustrated circuit includes 2⁸ =256 resistors R_(i) (i equals 0 to255), 2⁴ =15 each of coarse and fine comparators M_(i) and N_(i) (iequals 1 to 15), and 2⁸ =256 voltage comparators A_(ij) (i equals 1 to16 and j equals 1 to 15) for comparing analog input voltage V_(in) withreference voltages V₀ to V₂₅₅. In one embodiment, semiconductor chip SPhas dimensions of 3.95 mm×5.35 mm.

A resistor layer RL of uniform width made of, for example, an aluminumevaporating film is formed on the surface of semiconductor chip SP.Resistor layer RL is formed in a zigzag pattern with sixteen parallelrows having turns between each row. In the embodiment of FIG. 6, onepair of adjacent straight line portions of resistor layer RL forms agroup, with each pair of rows spaced apart from adjacent pairs of rows.

Resistor layer RL comprises a series connection of resistors R₀ to R₂₅₅.Corresponding reference voltages V₀ to V₂₅₅ are developed atcorresponding points along resistor layer RL. In the illustrativeembodiment, each straight line portion of resistor layer RL correspondsto 2⁴ =16 resistors selected from resistors R₀ to R₂₅₅. Accordingly,each turn of resistor layer RL corresponds to a turn in the seriescircuit of resistors R₀ to R₁₅ depicted in FIG. 1. Reference voltagesV₁₆, V₃₂,...,V₂₂₄ V₂₄₀, are developed at each turn, corresponding toevery 2⁴ =16 step within resistor layer RL.

Voltage comparators A_(ij) are formed adjacent straight line rows ofresistor layer RL. Voltage comparators A_(ij) (i equals 2 to 15 and jequals 1 to 15) are positioned between adjacent rows of resistor layerRL. Voltage comparators A_(1j) and A_(16j) (j equals 1 to 15) are formedon the outer perimeter of resistor layer RL. Coarse comparators M₁, M₃,M₅, M₇, M₉, M₁₁, M₁₃ and M₁₅ are formed on the right hand side ofresistor layer RL, and are connected to the respective turns of resistorlayer RL. Coarse comparators M₂, M₄, M₆, M₈, M₁₀, M₁₂ and M₁₄ are formedon the left hand side of resistor layer RL, and are also connected tocorresponding turns of resistor layer RL. Fine bit comparators N₁ to N₁₅are arranged in a row parallel to the successive rows of resistor layerRL and adjacent comparators A.sub. 16j (j equals 1 to 15).

Lower bit encoder ENCN is positioned on semiconductor chip SP adjacentto fine bit comparators N₁ to N₁₅ and is coupled thereto. Coarse bitencoder ENCM is also formed on semiconductor chip SP and positionedadjacent coarse bit comparators M₁, M₃, M₅, M₇, M₉, M₁₁, M₁₃ and M₁₅.Constant current sources Q₀₀₁ to Q₀₁₅ are formed adjacent comparatorsA_(1j) (j equals 1 to 15). A clock generator P.sub.φ is also positionedon semiconductor pellet SP. Coarse bit encoder ENCM and fine bit encoderENCN supply signals to buffer circuits B_(M) and B_(N), respectively,from which upper and lower bits D₁ to D₈ are derived. Bonding pads (notshown) can be formed on semiconductor chip SP outside the regions ofcoarse and fine bit encoders ENCM and ENCN, and can be connected withbonding wires to buffer circuits B_(N) and B_(M).

When resistor layer RL is formed in a zigzag resistor pattern asdescribed above, an accurate analog-to-digital converter is producedsince reference voltages V₀ to V₂₅₅ are determined by the positions ofthe resistors R₀ to R₂₂₅.

FIG. 7 illustrates the connections of the elements of the 8-bitanalog-to-digital converter of FIG. 6. Resistor layer RL is formed onsemiconductor chip SP in a zigzag pattern of successive rows ofresistors, with coarse comparators M₁ to M₁₅ formed at the respectiveturns T between the rows of resistors forming layer RL. Small blackcircles c in voltage comparators A_(ij) correspond to the bases oftransistors Q₃ (see FIG. 3) to which the outputs of coarse comparatorsM₁ to M₁₅ are supplied.

Coarse comparators M₁ to M₁₅ in an analog-to-digital converter of thepresent invention are pure voltage comparators and are connected with awaveform shaping circuit, such as a Schmitt circuit. Coarse comparatorsM₁ to M₁₅ occupy relatively large areas on semiconductor chip SP ascompared to the other elements of the analog-to-digital converter. In anexemplary embodiment, coarse comparators M₁ to M₁₅ occupy about ninetimes as large an area as the voltage comparators A_(ij).

If, as illustrated in FIG. 8, coarse comparators M₁ to M₁₅ are arrangedin a single row on semiconductor chip SP, large gaps result between therows of resistor layer RL and voltage comparators A_(ij), no matter howclose comparators M₁ to M₁₅ are positioned. In accord with theembodiment of the present invention illustrated in FIGS. 6 and 7, whencoarse comparators M₁ to M₁₅ are formed at the turning points T ofresistor layer RL, no significant gaps exist between the rows ofresistor layer RL and voltage comparators A_(ij), so that the size ofsemiconductor chip SP can be appropriately reduced.

When encoders ENCM and ENCN are positioned on semiconductor chip SP asillustrated in FIGS. 6 and 7, semiconductor chip SP can be about 5.4 mmin width×4.0 mm in length, in one example.

If coarse comparators M₁ to M₁₅ are merely positioned at each turningpoint T of resistor layer RL, i.e., at both sides of resistor layer RL,for example, as illustrated in FIG. 9, where coarse comparators M₁ toM₁₅ are positioned on both sides of resistor layer RL, with signal linesS supplying the outputs of coarse comparators M₂, M₄, M₆, M₈, M₁₀, M₁₂and M₁₄ to coarse bit encoder ENCM, the long signal lines S createparasitic capacities which result in significant operating difficulties.

An analog-to-digital converter of the present invention has a wired-ANDbetween a collector of transistor Q_(m1) of voltage comparators M_(k)(where k equals 1 to 14) and a collector of transistor Q_(m2) and thesucceeding voltage comparator M_(k+1) (k equals 1 to 14). The AND outputis supplied to coarse encoder ENCM and transistor Q₃ of voltagecomparators A_(ij). With coarse comparators M₁ to M₁₅ formed on bothsides of resistor layer RL, signal lines S are reduced in length, sothat parasitic capacities are unlikely to pose a significant problem.

An analog-to-digital converter iin accord with the present invention hassmall power consumption and operates at high speed. Further, the size ofthe integrated circuit chip can also be significantly reduced.

Although specific embodiments of the present invention have beendescribed in detail herein with reference to the accompanying drawings,it is to be understood that the invention is not limited to thoseprecise embodiments, and that various changes and modifications may beeffected therein by one skilled in the art without departing from thespirit and scope of the invention as defined in the appended claims.

What is claimed is:
 1. An analog-to-digital converter for converting ananalog input signal to a digital output signal with m upper bits and nlower bits in a single step, comprising:a plurality of resistor meansconnected in a series circuit to a voltage source for establishing(2^(m+n) -1) reference voltages at corresponding points on said seriescircuit; (2^(m) -1) upper bit comparators for generating a pluarality ofupper output signals indicative of said m upper bits, each upper bitcomparator having a first input receiving said analog input signal and asecond input connected to a selected one of said points to receive thecorresponding reference voltage, adjacent ones of said selected pointsdefining therebetween groups of reference voltages; upper bit encodermeans responisve to said upper output signals for generating said mupper bits; (2^(n) -1) lower bit comparators for generating a pluralityof lower output signals indicative of said n lower bits and havingrespective first and second inputs; lower bit encoder means responisveto said lower output signals for generating said n lower bits; andswitch means including (2^(m+n) -1) switching elements each having afirst input receiving said analog input signal and a second inputreceiving a corresponding one of said reference voltages, the switchingelements receiving the reference voltages of said groups constitutingcorresponding groups of switching elements; said switch means beingresponsive to said upper output signals to enable a selected group ofswitching elements, and said enabled switching elements generating(2^(n) -1) complementary first and second switching signals supplied tosaid first and second inputs, respectively, of said (2^(n) -1) lower bitcomparators.
 2. The analog-to-digital converter of claim 1; wherein eachof said upper and lower bit comparators and said switching elements ofsaid switch means includes by a plurality of bipolar transistors.
 3. Theanalog-to-digital converter of claim 2; wherein said bipolar transistorsof each of said comparators and said switching elements of said switchmeans include a differentially connected pair thereof.
 4. Theanalog-to-digital converter of claim 1; wherein said resistor means arearranged in a configuration with at least two sides, and wherein atleast one of said upper bit comparators is positioned on each of saidsides of said resistor means configuration.
 5. The analog-to-digitalconverter of claim 4; wherein said resistor means configuration is azigzag pattern with at least one turn, and wherein at least one of saidupper bit comparators is positioned adjacent said at least one turn. 6.The analog-to-digital converter of claim 5, in which said two sides ofsaid resistor means configuration are opposed; and wherein said zigzagpattern comprises successive rows of resistor means with turns betweensaid rows, and alternate ones of said turns are positioned at saidopposite sides of said resistor means configuration.
 7. Theanalog-to-digital converter of claim 6; wherein said upper bitcomparators are coupled to said series circuit at said turns.
 8. Theanalog-to-digital converter of claim 7; wherein said rows of resistormeans are parallel.
 9. The analog-to-digital converter of claim 8;wherein said resistor means are formed as an integrated circuit on asemiconductor chip.
 10. The analog-to-digital converter of claim 9;wherein said lower bit comparators are formed as said integrated circuiton said semiconductor chip.
 11. The analog-to-digital converter of claim10; wherein said upper bit comparators are formed as said integratedcircuit on said semiconductor chip.
 12. The analog-to-digital converterof claim 8; wherein each of said comparators and said switching elementsof said switch means includes a plurality of bipolar transistors. 13.The analog-to-digital converter of claim 12; wherein said bipolartransistors of each of said comparators and said switching elements ofsaid switch means are arranged in a differentially connected pairthereof.
 14. The analog-to-digital converter of claim 1; wherein thenumber of said lower bits equals the number of said upper bits, and thenumber of said upper bit comparators equals the number of said lower bitcomparators.
 15. The analog-to-digital converter of claim 1 furthercomprising means supplied with said upper output signals for derivingswitch control signals indicative of said m upper bits, said switchcontrol signals being supplied to said switch means to control theselection of said groups of switching elements.
 16. Theanalog-to-digital converter of claim 15; wherein said switch controlsignals are also supplied to said upper bit encoder means.
 17. Anintegrated circuit analog-to-digital converter for converting an analoginput signal to a digital output signal with m upper bits and n lowerbits in a single step, comprising:a plurality of resistor meansconnected in a series circuit to a voltage source in a configurationhaving two opposed sides for establishing (2^(m+n) -1) referencevoltages at corresponding points on said series circuit; (2^(m) -1)upper bit comparators for generating a plurality of upper output signalsindicative of said m upper bits, each upper bit comparator having afirst input receiving said analog input signal and a second inputconnected to a selected one of said points to receive the correspondingreference voltage, adjacent ones of said selected points definingtherebetween groups of reference voltages, and said upper bitcomparators being connected to said points to lie in two sets on saidtow sides; upper bits encoder means responsive to said upper outputsignals for generating said m upper bits; (2^(n) -1) lower bitcomparators for generating a plurality of lower output signalsindicative of said n lower bits and having respective first and secondinputs; lower bit encoder means responsive to said lower output signalsfor generating said n lower bits; and switch means including (2^(m+n)-1) switching elements each having a first input receiving said analoginput signal and a second input receiving a corresponding one of saidreference voltages, the switching elements receiving the referencevoltages of said groups constituting corresponding groups of switchingelements; said switch means being responsive to said upper outputsignals to enable a selected group of switching elements, and saidenabled switching elements generating (2^(n) -1) complementary first andsecond switching signals supplied to said first and second inputs,respectively, of said (2^(n) -1) lower bit comparators.
 18. Theanalog-to-digital converter of claim 17; wherein said resistor meansconfiguration is a zigzag pattern with at least one turn, and wherein atleast one of said upper bit comparators is positioned adjacent said atleast one turn.
 19. The analog-to-digital converter of claim 18, inwhich said two sides of said resistor means configuration are opposed,and wherein said zigzag pattern comprises successive rows of resistormeans with turns between said rows, said points being positioned at saidturns, and alternate ones of said turns being positioned at saidopposite sides of said resistor means configuration such that said upperbit comparators lie in alternating fashion on said opposite sidesadjacent said turns.
 20. An analog-to-digital converter formed as anintegrated circuit on a semiconductor chip for converting an analoginput voltage to a digital output signal with m upper bits and n lowerbits in a single step, comprising:a plurality of resistor meansconnected in a series circuit and connected to voltage source forproducing (2^(m+n) -1) step reference voltages, said step referencevoltages being ordered in (2^(m) -1) sequential groups each having arepresentative step reference voltage, and said series circuit beingarranged to lie in a folded pattern of sections, with turning pointsbetween adjacent sections; (2^(m+n) -1) voltage comparison means eachreceiving a respective reference voltage; (2^(n) -1) first voltagecomparators formed at and connected to respective turning points, eachof said first voltage comparators receiving said analog input voltageand one of said representative step reference voltages for comparisontherebetween and ordered in accordance with the group including therespective step reference voltage, each first voltage comparatorproducing first and second complementary outputs; means for adding thefirst output of each first voltage comparator with the second output ofthe next higher order first voltage comparator to produce respectiveadded outputs; (2^(m) -1) second voltage comparators; first encodermeans responsive to said added outputs to derive the upper m bits ofsaid digital output; means responsive to said added outputs forselecting a group of said voltage comparison means corresponding to avalue of said m upper bits, each of said voltage comparison means withinthe selected group comparing its respective step reference voltage withsaid analog input voltage producing compared outputs; said secondvoltage comparators being responsive to said compared outputs forproducing output signals; and lower encoder means responsive to saidoutput signals for deriving said lower n bits of said digital output.21. The analog-to-digital converter of claim 20; wherein said bipolartransistors of each of said upper and lower bit comparators and saidmeans for supplying include a differentially connected pair thereof. 22.The analog-to-digital converter of claim 20, wherein said first voltagecomparators are divided into two groups, and are formed at positionscorresponding to said turning points of said series circuit on oppoistesides of said circuit.
 23. The analog-to-digital converter of claim 20,wherein said voltage comparison means and said first and second voltagecomparators respectively include bipolar transistors.
 24. Theanalog-to-digital converter of claim 23, wherein said first voltagecomparators function as primary comparators for said second voltagecomparators.
 25. The analog-to-digital converter of claim 23, whereineach of said voltage comparison means and said first and second voltagecomparators are respectively formed of differential bipolar transistorpairs.